In a cache memory system, data stored in a volatile or non-volatile memory device may be cached in a faster access memory device having less space. For instance, data from a slower access main memory device in a system may be cached in a faster access L1 cache that is resident on the processor or L2 cache that is resident on the motherboard. In an associative cache, bytes at memory addresses in the slower access memory device are associated with different cache lines in the faster access device. In prior art cache systems, if a read request is directed to data in the slower access device that is available in the faster access cache, then the requested data is returned from the faster access cache, improving read access performance. However, in prior art write back cache systems, if the cache location for the requested data does not include the requested data and instead includes updated data to a different memory address, then the updated data in cache is written back to the slower access memory device and the requested data is fetched from the slower access memory device to return to the read request and to store in the cache in anticipation of future read accesses.
If a write request is directed to data in the slower access device that is available in the faster access cache, then the write data is written to the cache location for the write data, improving write performance. However, in prior art write back cache systems, if the cache location for the data to update with the write does not include the data to update and instead includes updated data to a different memory address, then the updated data already in cache is written back to the slower access memory device and the data in the write request is written to the cache. Further, before writing the data to cache, the data subject to the write request may be fetched from the slower access memory device to the cache before the write is applied.
In prior art write back systems, data that is frequently accessed and maintained in cache may be written back to the main memory device in response to write or read requests to other memory addresses that are cached at the same cache location. Such frequently requested data that is written back will likely have to be re-fetched back into cache in response to another request for the data. Substantial cache resources must be consumed to continuously prefetch frequently accessed data that is removed and returned to cache.